FIG. 1 is a schematic circuit diagram illustrating a conventional memory cell array and sense amplifier structure of a semiconductor memory device.
As shown therein, cell arrays CA0 through CAn each include a folded bit line structure in which memory cells are arranged at the intersections between every other one of word lines WL0 through WLn and bit lines BL1, /BL1, . . . , BLn, /BLn.
Odd pairs of bit lines BL and /BL are connected to multiple sense amplifiers SA arranged in a circuit unit above the cell array CA0, through block selection switches 3 and 4. The bit lines BL and /BL are also connected, through bit line pre-charge switches 1 and 2 with a pre-charge voltage VBLP line and a supply unit (not shown).
Even pairs of bit lines BL and /BL are connected with corresponding sense amplifiers SA arranged in a circuit below the cell array CA0, through block selection switches 3 and 4. The bit lines are connected to a pre-charge voltage supply unit (not shown) by pre-charge line VBLP through bit line pre-charge switches 1 and 2. The gates of the switches 1 and 2 are connected to a pre-charge control line BA.
The neighboring cell arrays CA include common sense amplifiers SA, i.e., there is an array of sense amplifiers between each pair of cell arrays. The above-described cell arrays CA are connected in a multiple cell structure, for thus forming multiple cell arrays.
FIG. 2 is a schematic detailed circuit diagram illustrating a sense amplifier circuit as shown in the circuit of FIG. 1.
As shown therein, there are provided a PMOS transistor PM1, a first NMOS transistor NM1 and a second NMOS transistor NM2 which are connected in series between a voltage Vcc and a ground voltage Vss. The source of the transistor PM1 is connected to Vcc and the drain is connected to both the signal line SPC and the source of the transistor NM1. The drain of the transistor NM1 is connected to signal line SNC and the source of the transistor NM2. The drain of the transistor NM2 is connected to ground. The gate of the PMOS transistor PM1 is connected to the signal SPE. The gate of NMOS transistor NM2 is connected to signal line SNE. The gate of transistor NM1 is connected to signal line SAEQ. For NMOS transistors NM1 and NM2, a plurality of sense amplifiers SA are connected in parallel between the common drain SPC of the PMOS transistor PM1 and the common drain SNC of the NMOS transistor NM2.
The operation of the conventional cell array and sense amplifier structure will now be explained with reference to FIGS. 1 through 3H.
First, the block selection switches 3 and 4 are turned on by a high level block selection signal BS0 as shown in FIG. 3C. The occasion that the cell array CA0 is selected will now be explained.
When a row address strobe signal /RAS (which activates the DRAM) is a low level (as shown in FIG. 3A), a corresponding word line WL0 becomes high level (as shown in FIG. 3B), so that the data from the memory cells connected with the word line WL0 are carried on the bit line connected with the memory cells.
The bit line pre-charge switches 1 and 2 are turned off by a low level bit line pre-charge signal BPO (as shown in FIG. 3D), so that the bit lines carrying the data from the accessed memory cells are not pre-charged.
Therefore, the data carried on the bit lines are inputted into the sense amplifiers SA connected in the circuit units arranged above and below the cell array CA0 through the block selection switches 3 and 4.
As shown in FIGS. 3E and 3F, if the sense amplifier PMOS transistor enabling signal SPE and the sense amplifier equalizing signal SAEQ are both at the low level, and the sense amplifier NMOS transistor enabling signal SNE is at the high level, the PMOS transistor PM1 and the NMOS transistor NM2 of the sense amplifier controller are turned on, and the NMOS transistor NM1 is turned off, so that the P side drain line SPC, as shown in FIG. 3G, becomes the high level (Vcc), and the N side drain line SNC becomes the low level (Vss).
Therefore, the sense amplifiers SA connected in the circuit units arranged above and below the cell arrays SA0, as shown in FIG. 3H, are activated, and the sensing operation of the data carried on the bit lines is performed.
If the signal /RAS becomes a high level, the word line WL becomes low level, for thus blocking the output of the cell data, and the bit line pre-charge switches 1 and 2 are turned on by a high level bit line pre-charge signal BPO, so that the bit lines are pre-charged to a bit line pre-charge voltage VBLP.
In addition, if the sense amplifier PMOS transistor enabling signal SPE and the sense amplifier equalizing signal SAEQ are both at a high level, and the sense amplifier NMOS transistor enabling signal SNE is at a low level, the NMOS transistor NM1 is turned on, so that the drain lines SPC and SNC, as shown in FIG. 3G, are equalized to the bit line pre-charge voltage VBLP.
However, in the conventional cell array and sense amplifier, since the bit line pairs of the bit line BL and the bit line /BL neighbor each other, coupling noise may easily occur therebetween.
Namely, if the word line WL is at the high level, the charges from the activated cells move along the bit line BL. At this time, if the neighboring reference bit lines /BL are influenced by the coupling capacitance, the voltage difference between the bit lines BL and the bit lines /BL is decreased, so that tolerance of noise is reduced during data sensing, i.e., sensitivity to noise increases.
In addition, as the data storage capacity of the DRAM is increased, and as the spacing between the bit lines is decreased, the above-described problems become more exaggerated.